1. Field of the Invention
The present invention relates to a technology of detecting amorphous silicon (a-Si) residue defects in a process of manufacturing array substrate, and in particular to a pixel layout structure for raising the capability of detecting amorphous silicon residue defects and method for manufacturing the same.
2. The Prior Arts
In the process of manufacturing Liquid Crystal Display (LCD), the manufacturing of an entire display is achieved through a first section Array manufacturing process, an intermediate section Cell manufacturing process, and a last section Module manufacturing process. The Array manufacturing process includes at least five stages comprising a Gate Electrode (GE) forming stage, a Semiconductor Electrode (SE) forming stage, a Source & Drain Electrode (SD) forming stage, a Contact Hold (CH) forming stage, and a Pixel Electrode (PE) forming stage. The mask used by each of the stages as mentioned above requires going through the processes of filming, lithography, etching, and peeling. These processes need to be repeated for five times in order to form a thin-film-transistor (TFT) array substrate.
Up to the present, a conventional thin film liquid crystal display is composed of a thin film transistor (TFT element switch) made of an a-Si layer, a storage capacitor (Cst), and a transparent conductive electrode made of ITO or IZO. While a voltage difference is applied between an upper and a lower substrate, liquid crystal would be driven by the voltage difference in producing an optical rotation effect. As such, the slant angle of liquid crystal is realized through the applied voltage, and in conjunction with a color filter having an array-type light source of red, green, and blue colors and the signal controlling over each gate line and data line, a pixel coupled with the assigning light would produce single colored spot, thus a planar display color effect is created through the combination of these pixels with various colored spots. When defects occur in a pixel, a voltage difference cannot be stably maintained between an upper substrate and a lower substrate to drive liquid crystal in producing optical rotations, so that the pixels on a planar display will present distributions of uncontrollable bright spots and dark spots or even gray spots, thus degrading the image display quality of a liquid crystal display. For this reason, liquid crystal displays are subject to severe electrical property tests before they can be delivered to customers.
An automatic Array Tester has a main function focusing on the electrical property test of an active area, and that is used to discover various defects produced in a manufacturing process. For an Array Testing, an a-Si residue means the pixel defects caused by certain drawbacks occurring in an a-Si layer manufacturing process, such as foreign materials before a-Si deposition, poor quality of a-Si layer development, and residue of a-Si etching etc., and that is also a major bottleneck affecting the yield rate of an Array manufacturing process. When an a-Si residue 10 occurs in a pixel and overlaps with a data line 12 as shown in FIGS. 1A & 1B, analyzing its pixel circuit diagram as referred in FIG. 1C, each pixel includes a transistor (TFT), a storage capacitor (Cst), and a parasitic capacitor (Cgd); and due to the existence of a-Si residue 10, therefore a capacitor CAS-ITO exists due to the a-Si residue overlapping with ITO. From the above discussion it can be discovered that, the voltage drop VAS-Residue resulted from the a-Si residue 10 existing in a pixel is proportional to the area of a-Si residue 10 (related to CAS-ITO) and voltage (VData) as supplied by a data line 12.
In a normal testing condition, the test capability may decrease significantly depending on the decreasing sizes of areas of a-Si residues. In case that the area of a residue is larger than ⅓ of a pixel area, then the chance for detecting the residue may reach 95%; if the area is less than ⅓ but larger than 1/24 of a pixel area, the chance of detection may range between 70-95%; otherwise in case that the area is less than 1/24 of a pixel area, then the chance for detecting the residue may drop below 50%. For an ordinary testing capability, it would not be easy to detect the pixel defect caused by the a-Si residue in an Array manufacturing process in case that the residue area is less than ⅓ of a pixel area, therefore, some pixel residue defect could have originally had a chance of being detected and repaired to normal status in an Array manufacturing process, failing detection and repair would make the unrepair defect flow to a subsequent manufacturing process, such that the pixel defect can only be detected in a Cell manufacturing process and repaired to become a dark spot, even more, the defect would be remained and flow into the last Module manufacturing process to become a bright spot defect.
Furthermore, in case that an a-Si residue pixel defect is detected in a subsequent Cell manufacturing process instead of being detected and repaired in an Array manufacturing process, it would cause more loading to a Cell repair and cassette transportation. In case that an a-Si residue pixel defect is not detected and repaired in both the Array manufacturing process and Cell manufacturing process, yet it is detected in a Module manufacturing process, these panels may not be repaired any more due to the bright spots defects formed by the a-Si residue in pixel, further resulting in downgraded panel products and increasing the risk of panel quality degradation. Or even worse, in case that the produced panels having a-Si residue pixel defects are delivered to the customers without being detected and repaired in any stage of the Array manufacturing process, the Cell manufacturing process, and the Module manufacturing process, it would result in instability, unreliability of panel quality control, and putting the credibility of the entire panel quality control in question.